The peripheral circuitry of a semiconductor memory array often includes a charging capacitor coupled between a reference voltage and ground. The stored charge of the charging capacitor is passed through the word line decoding circuits and word line detection circuits to charge the reference capacitors of the memory cells of the word line or word lines selected by the decoding and detection circuits. Because the charging capacitor must provide a reference voltage to each word line in the memory array, the charging capacitor often has a large surface area and is prone to failure upon the application of a sufficiently high voltage differential across the plates of the charging capacitor. The charging capacitor may also be coupled to ground from an oxide layer common to other components of the semiconductor memory array, including the gates of transistors in the memory. As a result, failure in these other components also connected between the common oxide layer and ground will result in failure of the charging capacitor as well.
Conventionally, the charging capacitor is biased during operation and testing by placing a reference voltage at the anode of the capacitor and grounding the cathode of the capacitor. During the testing of DRAM semiconductor memories, the voltage level applied to the word lines of the memory array is raised for an extended period. During burn-in testing, for example, the voltage applied to each word line is elevated from a normal level to a higher voltage for an extended period, possibly 20 hours or longer. Other testing modes are possible, including operating-life testing. As compared to the voltage applied during burn-in testing, the voltage applied to the word lines during operating-life testing is lower but is applied for a longer period, possibly 1000 hours or longer. Burn-in testing and operation-life testing are necessary to insure an adequate length of operating life for the semiconductor memory device. Each of these testing modes employs accelerated operating conditions over shorter period to simulate the effects of normal operating conditions over a longer period.
Because the charging capacitor may share the same oxide layer as the gates of the memory array, the elevated voltages applied to the word lines of the memory array during testing are also applied to the anode of the charging capacitor during the entire testing sequence. Thus, imperfections in the oxide layer shared between the transfer gates and the charging capacitor are often manifested in a failure of the charging capacitor. Unlike each word line of the semiconductor memory array, however, the charging capacitor is stressed during the entire testing sequence as the entire elevated testing voltage is applied at the anode of the charging capacitor, often resulting in excessive failure rates of the charging capacitor due to inadequate testing parameters.